1. Field of the Invention
The present invention relates to a read-out circuit in a semiconductor memory device for reading a multilevel data of three or more levels from selected memory cells in a memory cell array where a number of multilevel data storable memory cells are arranged in an array.
2. Description of the Related Art
A typical read-out circuit in a semiconductor memory device is provided for supplying a selected memory cell to be accessed for reading a data with electric current, comparing the (cell) current depending on the data to be read with a reference current to judge whether the cell current is greater or smaller than the reference current, and reading out the data from the selected memory cell in response to the result of the comparison. This technique for reading a data through judging the size of a cell current is called a current-sense method. It is known, for example, in a semiconductor memory device of two-level type where each memory holds one bit of data that two different memory states, where the cell current is great (i.e., the data is expressed by “1”) and small (i.e., the data is expressed by “0”), are predetermined as shown in FIG. 7 and the reference current is set at the intermediate between the two cell currents for their respective memory states for use to read one bit of data. In common, the reference current may be produced with the use of a reference memory cell formed in the same way as each memory cell to be accessed. Alternatively, instead of direct comparison between the cell current and the reference current, another technique is known where the degree of the cell current is indirectly compared with the reference current, in which the cell and reference currents are first subjected to current-voltage conversion, respectively, and then compared with one another. Hereinafter, this technique is referred to as a voltage-sense method, for descriptive purposes, as opposed to the current-sense method.
For responding to the demand of increasing the storage size and minimizing the cost of the production, a variety of multilevel data storable semiconductor memory devices have been developed as mass-storage semiconductor chips for storing three or more levels (e.g., two bits) of data in each memory cell. For example, a four-level data storable semiconductor memory device is provided where two bits of data are stored in each memory cell. As shown in FIG. 3, the cell current is classified into four different states between which three different intermediates of the reference current are allocated thus to read the four two-bit data by comparing the cell current with the three intermediates. For storing n-bit data in each memory cell, such a type of the multilevel data storable semiconductor memory device employs 2n different states of the cell current and (2n−1) states of the reference current.
It is common that the multilevel semiconductor memory device is narrower in the range of the current for identifying one level (memory state) than a two-level semiconductor memory device. There will hence be difficult for physically sparing a generous margin of difference between the cell current and the reference current. If the difference between the cell current and the reference current is too small, it may fail to permit a significant freedom of action in the read-out circuit. Also, there are two or more steps of comparing between the currents needed for reading out the data. These steps may be carried out in two different manners, a parallel-sense method where they are conducted in parallel and a time-division sense method where they are conducted in a sequence. An example of the parallel-sense method is disclosed in Japanese Patent Laid-Open Publication No. 2004-63018 (referred to as Citation 1 hereinafter). An example of the time-division sense method is disclosed in Japanese Patent Laid-Open Publication No. H10-501361 (referred to as Citation 2 hereinafter).
While the example of the parallel-sense method is substantially equal in the duration of time required for the comparison to a two-level data storable semiconductor memory device, it has to provide a number of sense circuits for the comparison which is identical to the number of the reference currents in each memory cell to be accessed. Accordingly, the read-out circuit will be enlarged in the installation area and disadvantageously increased in the production cost. For example, in the four-level data storable semiconductor memory device where a two-bit data is stored in each memory cell, twenty four of the sense circuits are needed for reading 16 bits of data because the number of memory cells to be accessed at the same time is eight and the reference current to be used has three different states. Considering the fact that the two-level data storable semiconductor memory device requires sixteen of the sense circuits, using the parallel-sense method increases the installation area of the read-out circuit of the four-level data storable semiconductor memory device in comparison with the two-level data storable semiconductor memory device.
On the other hand, the time-division sense method requires only one sense circuit for the comparison in each of memory cells to be accessed at the same time, thus minimizing the increase of the installation area of the read-out circuit. For example, in the four-level data storable semiconductor memory device where a two-bit data is stored in each memory cell, eight of the sense circuits are needed for reading 16 bits of data because the number of memory cells to be accessed at the same time is eight. Accordingly, the four-level data storable semiconductor memory device will hence be smaller in the installation area of the read-out circuit than the two-level data storable semiconductor memory device. Although being advantageous in the installation area of the read-out circuit, the time-division sense method causes an n-level data storable semiconductor memory device where n bits of data are stored in each memory cell to be subjected to the time division process for the comparison at least n times, thus lengthening the read-out action.
An example of the time-division sense method will now be explained briefly where a four-level data of two bits per cell is read out, referring to FIG. 8. FIG. 8 is a circuitry diagram schematically showing an arrangement of the read-out circuit in a conventional semiconductor memory device using the time-division sense method as well as the voltage-sense method. The memory cells shown in FIG. 8 are of a flash memory type having the floating gate structure.
As shown in FIG. 8, the read-out circuit 50 using the time-division sense method includes a current loading circuit 51 for feeding a voltage to the drain of a selected memory cell 57 to be accessed to produce a read-out current (cell current) depending on the memory state and another current loading circuit 52 for feeding a reference current to reference memory cells 58 to 60. The selected memory cell 57 is electrically connected at the drain to the current loading circuit 51 by a sense line 61. The current loading circuit 52 is electrically connected with a reference line 62. The current loading circuit 51 has a current-voltage conversion function along the sense line 61 for converting the cell current into a read-out voltage while the current loading circuit 52 has a current-voltage conversion function along the reference line 62 for converting the reference current into a reference voltage. The sense line 61 and the reference line 62 are connected to two differential input ports of a sense amplifier 53 respectively for amplifying and releasing a difference of the potentials between the sense line 61 and the reference line 62 (that is, a voltage difference between the read-out voltage and the reference voltage). The output port of the sense amplifier 53 is connected to a first data latch circuit 54 for latching the result of a first sensing action and a second data latch circuit 55 for latching the result of a second sensing action. The data latch circuits 54 and 55 temporarily retain the data released from the sense amplifier 53. When the data retained in the second data latch circuit 55 is defined, the first data latch circuit 54 and the second data latch circuit 55 release their respective latch output signals 63 and 64 for allowing a two-bit data to be read out from the selected memory cell 57. Also, during the sense action, the latch output signal 63 of the first data latch circuit 54 is delivered to a selector circuit 56 which in turn conducts a switching action to connect the reference line 62 to any of the three reference memory cells 58 to 60 which are different in the reference current.
In the case of using the time-division sensing method in the conventional multilevel data storable semiconductor memory device employing the voltage-sense method as described above, the I-V relationship between the reference voltage and the reference current in the four-level data storable semiconductor memory device where a two-bit data is stored in each memory cell will be described as an example, referring to FIG. 9. The I-V relationship between the reference voltage and the reference current represents a linear characteristic where the value of the reference current is varied in proportion to the reference voltage and a saturated characteristic where the value of the reference current remains not varied when the reference voltage changes for each of three intermediate reference currents L, M, and H designated between the four different levels of the data. It is also assumed that the reference memory cells assigned with the three reference currents L, M, and H are different in the current drive capability. Moreover, the I-V relationship between the reference voltage and the reference current shown in FIG. 9 is based on the fact that the load in the current loading circuit is a common resistance.
As apparent from FIG. 9, the values of the reference current and the reference voltage are determined for each of reference currents L, M, and H at the intersection (action) point of the I-V characteristic and the load characteristic of the current loading circuit respectively. The reference voltage for each of reference currents L, M, and H as shown in FIG. 9 corresponds to a supply voltage input from the reference line 62 to the sense amplifier 53 shown in FIG. 8, indicating the action point of the sense amplifier 53.
Generally speaking, the action point of the sense amplifier employing the voltage-sense method has a nonlinear characteristic, where the margin for the read-out action can be increased by increasing the rate of amplification of the voltage in a limited range about the action point. However, when the multilevel data storable semiconductor memory device employs the time-division sense method, its sense amplifier is provided for each memory cell and its reference voltages are different depending on their corresponding reference currents. This allows the action point of the sense amplifier to be varied with the reference current. It will hence be difficult to optimize the margin of action during the comparison between the reference voltage and the read-out voltage at each reference current. On the other hand, the parallel sense method which is disadvantageous in the installation of area includes the sense amplifier for each reference current and can thus optimize the action point of the sense amplifier separately.